Senior Hardware Verification Engineer

Our client is seeking a highly skilled and experienced Senior Hardware Verification Engineer to join their innovative team in **San Francisco, California, US**. This role offers a hybrid work arrangement, combining the benefits of in-office collaboration with the flexibility of remote work.

The Senior Hardware Verification Engineer will be responsible for developing and executing comprehensive verification strategies for complex digital hardware designs. You will work closely with the design team to ensure the functional correctness, performance, and robustness of our client's cutting-edge integrated circuits (ICs). This involves creating test benches, developing constrained-random verification environments, implementing coverage models, and debugging simulation failures. The ideal candidate possesses a deep understanding of digital logic design, verification methodologies (e.g., UVM), and scripting languages.

Key responsibilities include:
Developing and implementing robust verification plans for complex ASIC/SoC designs. Creating verification environments using SystemVerilog and UVM (Universal Verification Methodology). Writing test cases, stimulus generation, and assertions. Developing and utilizing coverage models to ensure thorough verification. Debugging simulation failures and collaborating with design engineers to resolve issues. Performing functional simulation, gate-level simulation, and timing analysis. Participating in architectural reviews and providing feedback on design for verifiability. Staying current with the latest verification methodologies and tools. Mentoring junior verification engineers and sharing technical expertise. Contributing to the development of reusable verification IP and testbench infrastructure. Collaborating with cross-functional teams, including firmware and software engineers.
The successful applicant will hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. A minimum of 7 years of experience in hardware verification is required. Proven expertise in SystemVerilog and UVM is mandatory. Strong understanding of digital design principles, Verilog/VHDL, and standard verification flows is essential. Experience with scripting languages (e.g., Python, Perl, Tcl) is highly desirable. Excellent problem-solving, analytical, and communication skills are crucial for this role. This is a great opportunity to contribute to high-impact projects in **San Francisco, California, US**.

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